AnsweredAssumed Answered

AD9783

Question asked by DSpamp Employee on Jun 21, 2018

We plan to use an FPGA DDR interface to drive the AD9783. I assume that this is commonly done because of the speed as well as the fact that the interleaved data is clocked on both rising and falling edges of the clock. Can you provide information (possible an app note) on other projects that have used this approach for guidance?

Outcomes