I am experiencing some highly intermittent SPI read issues between a PIC MCU and an ADAU1452 in a client system. When I finally managed to capture an erroneous read, examination of the SPI waveforms appeared to show the DSP behaving as if it saw an extra SCLK cycle - the MISO line came out of tristate one cycle too early, during the last bit of the address write. Clearly this will lead to spurious results as the read address will be incorrect.
Anyway, the obvious starting point is to double-check the PIC's SPI mode settings. Thing is, the ADAU145x datasheets is contradictory about the settings that the DSP requires. The timing data (Figure 9, p14 of datasheet) clearly shows SCLK as being idle-low and data being read on the rising edge, which I believe is called SPI mode 0 (CPOL = 0, CPHA = 0).
However, the description of the Slave Control Ports on p38 of the datasheet states that SPI Mode 3 (CPOL = 1, CPHA = 1) is required, i.e. SCLK idle-high. Figure 35 on p38 is ambiguous because it shows both options but is not clear about whether the Mode 0 waveforms are highlighted to show they are correct, or greyed-out to indicate that they are not used.
At the moment, my PIC is set up to use SPI Mode 3. I don't know whether incorrect SPI settings are the cause of my problem, but I would like to rule out the possibility one way or the other. Can anyone from ADI give a definitive answer as to what the ADAU145x wants to see? (Of course, any insight into other reasons for occasional SPI read glitches would also be gratefully received!)