Hi, I'm engaging in a somewhat odd behavior in that I need a time stable alignment between the two chips on an FMCOMMS5 while tuning them to different frequencies.
I went through the MCS procedure which appears to be
1) put the chips in alert from fdd
2) for n = 1:5 write n to multichip_sync on the slave device, then the master device
3) put the chip back to fdd.
I then tune the master device to F0 and the slave device to F1. I would imagine due to sharing the same reference clock they would be at least time aligned. This appears to not be the case. Using a coherent reference source (fed by the same clock), I'm seeing massive frequency offset. This should not be the case.
We have modified the default FPGA with our own internal DSP which I have verified is not the cause of the problem. Any ideas? Am I missing something simple?