We're trying to enable digital gain in the AD9361 while using a split gain table and fast attack AGC. Register 0x0FB is set to 0x44 to enable digital gain, and register 0x100 is set to 0x2f to set the step size and maximum digital gain. However, we're seeing two things that make us think the digital gain is not working.
1. The Rx2 (we're connected to Rx2 only) digital gain index at 0x2b7 always reads 0x00. We even configured our FPGA to read this register continuously during a receive and it never changes.
2. We should be able to force Rx2 digital gain by writing register 0x10e. However, bits 4:0 can not be written to any value other than 0. Bit 5 can be set or cleared.
Are there any other requirements for enabling digital gain than setting these two registers?