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How do I trigger BF548 EPPI from software in GP0 TX/RX mode?

Question asked by adamhonse on Jun 18, 2018
Latest reply on Jun 28, 2018 by Jithul_Janardhanan

I'm having trouble configuring the EPPI interface on a BF-548 processor.  I want to use the interface to sample 4 to 8 inputs at high speed using DMA for a sort of bit-banging input application where I periodically process the received data.  I'm using the General Purpose 0 Frame Sync (GP0) mode as frame sync isn't important in my application.  I want the EPPI to sample at a constant rate so I've set the CLKDIV to a conservative value for testing and set the IFSGEN and ICLKGEN bits in the EPPI Control register.  I configured word length to 8 bits.  I've configured the corresponding DMA (DMA12 for EPPI0, DMA13 for EPPI1) for single-shot transfer with a buffer of 512 bytes, 16 bit word size, with X_MODIFY set to 2 to match the 16 bit word size.  To test the control flow of my code, I am trying to get the port to transfer data out of the EPPI instead of input it, as I can see the output on my scope to confirm it is working.  The basic control flow of my code looks like this:


EPPI0_CLKDIV = 0x289 (should be 200KHz)

EPPI0_CONTROL = 0x0000460E

DMA12_START_ADDR = 0xFF8033BC (pointer to my 512 byte buffer)

DMA12_NEXT_DESC_PTR = 0x00000000 (not using descriptors)

DMA12_X_COUNT = 0x0200 (512 bytes)

DMA12_X_MODIFY = 0x0002 (2 byte words)

DMA12_Y_COUNT = 0x0000

DMA12_Y_MODIFY = 0x0000

DMA12_CONFIG = 0x0005 (DMA Enable, Word Size 16, STOP flow control)


At this point, DMA12_CURR_X_COUNT is set to 0x01FC, so 4 words have been transferred.  I assume this is into the DMA FIFO.  Next, I set the enable bit in the EPPI0_CONTROL register:


EPPI0_CONTROL = 0x0000460F


Stepping over this line shows that DMA12_CURR_X_COUNT updates to 0x01DC and the DMA12_CURR_ADDR increments as well.  This corresponds to 32 additional words transferred, which I'm assuming is into the EPPI FIFO.


Now, my question is, how do I trigger the EPPI to perform the transfer?  The BF548 HRM suggests that GP0 TX is always triggered internally, and that this triggering occurs "as soon as the EPPI clock is enabled and synchronized".  I set the ICLKGEN bit so the clock should be generated internally, correct?  The next paragraph confused me.  "Care should be taken that the clock is enabled only after the EPPI FIFO becomes full."  This suggests I should not have the ICLKGEN bit set until after the FIFO is full (which seems to happen when enabling the DMA while the EPPI is also enabled) but the HRM also states "Once the EPPI is enabled, none of the MMRs should be changed.  If any change is required, the EPPI should first be disabled and then re-enabled..."  I tried that, but it seems disabling the EPPI resets the FIFO.  Upon disabling the EPPI, setting ICLKGEN, and then re-enabling the EPPI, the DMA moves 32 more words and stops, as if the FIFO has been cleared and is refilled.  Nothing comes out the EPPI pins.