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Cascading Multiple HMC7043

Question asked by mikaelis on Jun 18, 2018
Latest reply on Jun 26, 2018 by kpeker

Dear Forum (kpeker)

I am designing a similar system structure as the one explained in the article "SYNCHRONIZING SAMPLE
CLOCKS OF A DATA CONVERTER ARRAY". I've designed my own evaluation PCBs and I want to use one as the source HMC7043 and the two others cascaded behind the source HMC7043 in parallel (My final system will comprise a lot more HMC7043). I have a centrally generated, highly stable clock source that generates a Sample clock of 468 MHz and a continuous SYSREF of 19.5 MHz.

We'd like to operate the SYSREF signal in continuous mode at all the downstram devices (let's assume I want to drive 14 DACs in parallel. Each one is connected to one of the secondary HMC7043's outputs. In other words: I expect 14 SAMPLE clocks and 14 continuous SYSREF clocks at the outputs of my two parallel HCM7043 units and ALL continuous SYSREFS and ALL SAMPLE clocks are phase aligned.

 

I am doing this:

I configure all the HMC7043 boards exactly the same, register settings see below. The dividers for my SYSREF channels are set to 24 (468/24=19.5). the sysref timer is set to 192 in order to be below the 4 MHz margin (2.4MHz).

I am not using my centrally generated SYSREF to feed the SYNC input from the HMC7043 but instead I'm using a single pulse with a duration of 4*SAMPLE clock period. This pulse of course is genrated synchronously to the SAMPLE clock. i can generate this pulse manually and I expect this pulse to reset the HMC7043 internal counters to a defined state (0).

The secondary HMC7043 boards however, use the continuous SYSREF generated by the first HMC7043 as theis RF_SYNC inputs. In the HMC7043 article, this is also done.

 

What i observe:

I observe that which each assertion of the SYNC pulse, the SYSREF outputs of the secondary HMC7043s "jump" to a different phase. I expect this behaviour since the SYSREF is divided by 24. This means that the counters of the secondars HMC7043 boards are not reset at the same time.

 

 

Q0 (master question): How can I prevent this behaviour and how can I gurantee that upon assertion of a single "SYNC" signal, all the secondary HMC7043 SYSREF outputs will be phase aligned? Is it even possible with only these chips?

Q1: regarding the RFSYNC signal in the article: could you elaborate on how exactly the SYSREF signal is used to reset the HMC7043s in the setup described in the article?

Q2: Is the SYSREF pulsed or is it continuous?

Q3: What register settings are used for the Normal channels, the SYSREF channels and whats the value for the SYSREF Timer counter?

Q4: What exactly does the SYSREF timer do? I'm pretty sure there is some misleading information either in the data sheet or in the forum (I came across many questions regarding the sysref timer)

 

Best regards, mikael (still hoping kpeker will have a look at this )

 

%% HMC7043_CONFIG_DATA:
DATA =  [

'009F4D';
'00A0DF';
'00500F';
'005CC0'; % sysref TIMER: 192
'005D00';
'005A07';
          % configure channel 0 (normal channel)
'00C8F1';
'00C901';
'00CA00';
'00CB00';
'00CC00';
'00CD00';
'00CE00';
'00CF00'; % mux selection: 00=channel divider
'00D009';
           % configure channel 2 (normal channel)
'00DCF1';
'00DD01';
'00DE00';
'00DF00';
'00E000';
'00E100';
'00E200';
'00E300';
'00E409';

          % config channel 1 (sysref channel)
'00D2F1'; %FD
'00D318'; % divider = 24 (0x18)
'00D400'; % divider upper bits)
'00D500';
'00D600';
'00D700';
'00D800';
'00D900'; % 00 mux selection: 00=channel divider
'00DA09';

 

          % config channel 3 (2nd sysref channel)
'00E6F1';
'00E718'; % divider = 24
'00E800';
'00E900'; % fine analog delay
'00EA00'; % coarse digital delay 00=0
'00EB00';
'00EC00';
'00ED01'; % output mux: 01= from analog delay, 00 = channel divider
'00EE09';

          % soft reset
'000102';
'000100';

          % input buffer mode
'000A07'; % sync channel    07=AC, 08=DC
'000B07'; % normal channel

 

'000180'; % reseed request
'000184'; % pulse generator stream? i guess i dont need that???
'807D00'

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