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AD9361 DUAL PORT FULL DUPLEX MODE (CMOS) Timing

Question asked by jsusong on Jun 15, 2018
Latest reply on Jun 20, 2018 by srimoyi

I have an application that requires the AD9361 to be configured for 2R2T DUAL PORT FULL DUPLEX MODE (CMOS) and would like to know if it is possible to move the DATA_CLK (1MHz) edges closer to the center of the RX_FRAME and data signals?  The register settings and resulting waveform are shown below.

 

AD9361 Register

Description

Value

0x006

Rx Clock and Data Delay

0x0F

0x010

Parallel Port Configuration 1

0xCC

0x011

Parallel Port Configuration 2

0x00

0x012

Parallel Port Configuration 3

0x02

0x03B

Digital I/O Control

0xC3

 

 

DUAL PORT FULL DUPLEX MODE (CMOS) Timing

CH1 DATA_CLK

CH2 RX_FRAME

CH3 P0_D[2]

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