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ADBF561 PPI in Sync-less Tx Mode

Question asked by clim on Dec 23, 2011
Latest reply on Dec 29, 2011 by clim

Hi everyone,


I've been digging through the forums and reading all the datasheets and reference manuals and can't seem to get my PPI working in Tx mode. My DMA1_0_CONF = 0x75B4 and PPI0_CONTROL = 0x3822.


I took a look at the example code from the Video Input-Output project and modified a few things. I have 4 buffers which basically counts up from 0 to 127 (e.g., buffer0[0] = 0, buffer0[1] = 1,...,buffer1[0] = 32, buffer1[1] = 33, ............, buffer3[0] = 96, buffer3[1] = 97). I created a large descriptor array like the following:


tDMA_descriptor DMA_PPI0[4];


DMA_PPI0[0].NDPL = ((unsigned long int)&DMA_PPI0[1]) & 0xffff;
DMA_PPI0[0].NDPH = (((unsigned long int)&DMA_PPI0[1]) & 0xffff0000)>>16;
DMA_PPI0[0].SAL = ((unsigned long int)&buffer0) & 0xffff;
DMA_PPI0[0].SAH = (((unsigned long int)&buffer0) & 0xffff0000)>>16;


DMA_PPI0[1].NDPL = ((unsigned long int)&DMA_PPI0[2]) & 0xffff;
DMA_PPI0[1].NDPH = (((unsigned long int)&DMA_PPI0[2]) & 0xffff0000)>>16;
DMA_PPI0[1].SAL = ((unsigned long int)&buffer1) & 0xffff;
DMA_PPI0[1].SAH = (((unsigned long int)&buffer1) & 0xffff0000)>>16;


DMA_PPI0[2].NDPL = ((unsigned long int)&DMA_PPI0[3]) & 0xffff;
DMA_PPI0[2].NDPH = (((unsigned long int)&DMA_PPI0[3]) & 0xffff0000)>>16;
DMA_PPI0[2].SAL = ((unsigned long int)&buffer2) & 0xffff;
DMA_PPI0[2].SAH = (((unsigned long int)&buffer2) & 0xffff0000)>>16;


DMA_PPI0[3].NDPL = ((unsigned long int)&DMA_PPI0[0]) & 0xffff;
DMA_PPI0[3].NDPH = (((unsigned long int)&DMA_PPI0[0]) & 0xffff0000)>>16;
DMA_PPI0[3].SAL = ((unsigned long int)&buffer3) & 0xffff;
DMA_PPI0[3].SAH = (((unsigned long int)&buffer3) & 0xffff0000)>>16;
DMA_PPI0[3].DMACFG = (DMA_CONF|0x1)&0x0011;


You may notice that the 4th descriptor sets the FLOW in DMA1_0_CONF to 0


The gist of my code is

1) Initialize buffers

2) Initialize PPI0 and DMA1_0

3) Enable DMA1_0 then PPI0

4) Wait till DMA1_0_IRQ_STATUS & DMA_RUN = 0

5) Disable PPI0 then DMA1_0


I haven't configured any clocks nor any interrupts. All I really want to show is that I can transmit data through PPI reliably to an FPGA. I have attached screen captures of the data coming out of the PPI data bus. In the first image, you may notice that there are a lot of places where the PPI bus is zero, is there a reason for this? In the second image (a zoomed up version of the first) you can see that the data sent is actually being sent twice which I suspect has to do with the clock rates I'm using however a more prominent issue is the fact that data 11 is missing ( it sends 8, 9, 10 and straight to 12). Can anyone explain why these things are happening? I would really appreciate it.


Thank you