I WANTED to implement ad9361 with intel Nios2 processor. How can i create qsys for it?
basically i have to design a small compct module for it.
please help me.
j s hyanki
We currently support cyclone V devices for interfacing the AD9361. What FPGA do you intend to use ?
You can start from the arradio design and modify it to fit your specific FPGA. For a base design based on Nios2, you can check our Arria 10 gx base design.
Have u integrate ad9361 ip with Nios2 in that?
if yes how?
We haven't integrated AD9361 with Nios2. Most of the drivers don't care about the processor, so they should compile fine for Nios2 or ARM. Some of the low level drivers need to be rewritten for the different SPI IP that will be used, but you should be able to use the Arria 10 GX related drivers for that with small adjustments, if it's the case.
We don't plan to create a AD9361 Nios 2 based design in the near future.
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