Could you help review below my AD6688 JESD204B register configuration , Thanks . We use 600M bandwidth ,so sample rate is 1.5GSPS .
1) We intend to connect ADC A and ADC B to different FPGAs , So each FPGA corresponds to a converter. Does it mean M=1 , ADCA to SERDOUT0±~SERDOUT3±,ADC B to SERDOUT4±~SERDOUT7± .
2)we selected 14 bit accuray , So N=16, N'=16
3)Although the AD6688 output supports 15.5 Gbps, the FPGA's JESD204B IP only supports 12.5 G bps, so we chose a rate less than 12.5 Gbps.
Lane rate = (M*N'*1.25*Fs)/L=1*16*1.25*1.5/L=30G/L<12.5 Get L=4, that is, 4 lanes per ADC output, each lane rate is 7.5Gbps .
4)If S=2, F=1 and K may be 20,24,28,32
Get LMFC = 3G/(2*K)=1/40,1/48,1/56,1/64 ADC clock
If you take S=4, then F=2, K may take 12,16,20,24,28,32
Get LMFC = 3G/K = 1/48, 1/64, 1/80, 1/96, 1/112, 1/128 ADC clock
Due to our PLL divider ratio limitation, we chose SYSREF as 1/40 ADC clock = 3G/40 = 75MHz clock
The parameter is selected as
L=4, M=1, F=1, S=2, HD=1, N=16, N'=16, CS=0, K=20
ADC clock=3GHz, sine wave
SYSREF=75MHz, square wave (AD9548 out)
FPGA JESD204B serdes and core clock is lane_rate/40=187.5MHz, square wave (AD9548 out)
The AD6688 outputs two ADCs to different lanes.
ADC A Output SERDOUT0±~SERDOUT3±
ADC B outputs SERDOUT4±~SERDOUT7±.