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Some Questions on AD9361 DMA ADC Data Format

Question asked by FRestuccia on Jun 14, 2018
Latest reply on Jun 15, 2018 by FRestuccia

Hi all,

I am trying to receive some IQ samples using the dac_capture() format provided in the No-OS drivers.

I have some questions:

 

1) In the main() function provided, there is the following piece of code:

#ifdef CAPTURE_SCRIPT
// NOTE: To prevent unwanted data loss, it's recommended to invalidate
// cache after each adc_capture() call, keeping in mind that the
// size of the capture and the start address must be alinged to the size
// of the cache line.
mdelay(1000);
adc_capture(16384, ADC_DDR_BASEADDR);

I don't understand why the adc_init() function is not called before adc_capture(). Shouldn't we initialize the DMA before transferring data?

2) I tried running the following:

 

mdelay(1000);
adc_init(ad9361_phy);
adc_capture(1, ADC_DDR_BASEADDR);

By then using the XSCT console on Xilinx SDK and typing mwr 0x00800000 0x0000 10, then running my code, and then typing mrd  0x00800000 10, I obtain the following:

 

 800000: FF13021C
800004: FDC9FF4F
800008: 00000000
80000C: 00000000
800010: 00000000
800014: 00000000
800018: 00000000
80001C: 00000000
800020: 00000000
800024: 00000000

Now: what does this data represent?

 

As far as I understand, the AD9361 has a 12-bit ADC but the samples we receive from the DMA are in 16-bit 2's complement format; I have seen that in the adc_init() function the ADC_FORMAT_BIT in the REG_CHAN_CNTRL is NOT set. And, the adc_init() function enables the ADC_FORMAT_SIGNEXT bit, so the bit sign should be extended.

 

If we have two channels, how are the I/Q samples orchestrated? 

 

I am assuming that they are orchestrated as I1-Q1, I2Q2 (please correct me if I am wrong). So in my case, I1 = 0xFF13, Q1=0x021C, I2=0xFDC9, Q2=0xFF4F. Therefore, the samples, interpreted as integers in 2-bit's complement, should be the following, I1=-237, Q1=540, I2=-567, Q2=-177. Now, assuming that this is the correct orchestration of I/Q samples and my calculations are correct, what is the quantity that I need to divide by these integers to get my I/Q samples in float format? 

Is it 2^12 or 2^11 (12 bits - 1 sign bit)?

 

Also, just to make sure I understand correctly, let's assume for simplicity that my RX sampling frequency is 2MS/s. If I read 500k samples using adc_capture(500000, ADC_DDR_BASEADDR), will I get all the I/Q samples sampled by the ad9361 in 0.25 seconds? 

 

Thank you.

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