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Matlab HDL BSP and Reference design updates

Question asked by ddk on Jun 13, 2018
Latest reply on Jun 20, 2018 by travisfcollins

Regarding the Matlab reference design ( GitHub - analogdevicesinc/MathWorks_tools: Scripts and tools created by ADI to be used with MATLAB and Simulink with ADI…  )


has the AXI bus version in the the reference design ( used by axi_ad9361_adc_dma ) changed from AXI4 to AXI3 ?


I can no longer set the DMA to transfer 8192 bytes per transfer (FIFO size - Bursts : 64, Bytes per burst : 128)
the max seems to be 4096 (Bursts : 32, Bytes per burst : 128) when using AXI3


a bit of background is that the IP core I'm getting data form provides frames to the DMA which need to be kept together.

I'm using the ZC702 with FMNCOMMS2