I have debug the FMC-AD9162 in 1x bypass mode for several weeks. The sample frequency was 4.5GSa. The signal frequency was 100MHz. My quension is why the power in the (fs/4 - 100MHz) and (fs/4 + 100MHz) is so high.How can i sovle this problem.
Are you using ADS7 + AD9162 Evb ?
I am using Xilinx KCU105 + AD9162 EVB.
Thank you for your reply. According to the datasheet of AD9162,Tabel 35 show ''When used in 1× bypass mode, the desired signal must be placed in the lower half of the first Nyquist zone, as in 0 to DAC clock ÷ 4 MHz''.Is this mean i can not use AD9162 to sample 1.6GHz sample in1xbypass mode when the sample frequency is 4.5Gsa?
Another quension is is why the power in the (fs/4 - 100MHz) and (fs/4 + 100MHz) is so high as the picture shown below.
You can use the signal at frequencies above DAC_CLK/4, as well. The problem is that, according to the following picture, if the signal is used out of this frequency range, due to less overlap of FIR85 and 1x interpolator filters, less power of the signal is getting to the output:
to answer the second part of your question, I can't see these spurs at the output of my DAC setup which consists of an ADS7-V2 FPGA board plus AD9162 eval board. It is possible that you are using a DAC_CLK/8 in your setup and the signal is mixed with this clock and finds its way into output spectrum. Try using an external clock for the DAC board and see if you can repeat the output again.
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