i found when AD9361 change from alert to TX status, the TX port can be seen a large ramp up power. is it the DAC steady process product or something wrong register setting? in order to see clearly, i send all zero I/Q to AD9361 TX data interface.
you can see that the pulse is start of alert to TX, and it's power is -30dBm, this pulse power will wrong trigger RX port AGC to wrong status.
after the pulse, the power of tx is return to normal status.
now the AD9361 work in TDD 1T1R mode, data interface half duplex, DDR mode. how to solve this issue?
i add one new snapshot to show pulse detail, and i change the TX frequency to 690M to clarity the TX PLL effect.
you can see that the pulse process time is about 20us;