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External Access in Delayed Branch Sharc 21369

Question asked by AstroMedGlen on Dec 22, 2011
Latest reply on Jan 2, 2012 by Mitesh



    I do not have a specific problem to report. But I think I am seeing a poterntial issue with external reads/writes in delayed branches. For example, I am not sure if the following external write is completed:


jump Some_Label (db);

    r0 = r0 + 1;

    dm(SOME_FPGA_ADDRESS) = r0;


when the AMICTLX regsiter corresponding to this address is set to:  WS7 | AMIEN | BW32.


I looked it the programming reference guide and did not see any delayed branch related restrictions for external accesses. I know that an external access like this is going to take several instruction cycles to complete. Is an instruction in a delayed branch not granted more than one instruction cycle to execute? Or does it even matter? Is the program pointer not held up for external writes?


Thank you,