I am trying to do a basic design before making a jump to the Microblaze. I have implemented the following block design in Vivado. I am using a ROM to store the data samples and a counter attached to it. The ROM is reading out the data samples to the Xilinx JESD204B IP core which is configured for 8 lanes per link. I am using the same configuration the other side i.e on the DAC. I am trying to interface Kintex-7 series (not Ultrascale) FPGA to AD9172 dual link DAC. I just want to test the design and hence I am going with this basic approach. Later, I plan to make the use of Microblaze Soft Core Processor and a BRAM. The problem now is I have implemented the design and have generated the bit file for it. I have programmed the FPGA and the AD9172 DAC EBZ board is attached to the FMC connector present on the board. I have configured the AD9172 for the same configuration Single link - Mode 11 i.e. 8 Lanes per link and in Subclass 1 mode. I have connected the signals as it appears in the design below and I am still not able to get the output on the DAC0. I am wondering whether I have made the right connections or am I missing some signals which are to be connected.
Clocking wizard output: 100 Mhz for clk_out1 and clk_out2. All other signals on the left side except the diff_clock_rtl are coming from the AD9172 DAC board. I am just connecting the jesd204_0 txp and txn to the SERDES +- 0 to 7. Please let me know if I am missing something.
I would appreciate the help.