The frequency range of the REF_CLK signal must be between 10 MHz and 1000 MHz
The external clock is used as the reference clock for the RFPLL and the Clocking PLL on the device and thus needs to be a very clean clock source. The inputs are biased on the device to a 618 mV voltage level.
Ensure that the external clock peak-to-peak amplitude does not exceed 2V, for phase noise requirements refer UG
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