I am trying to design a SP48T using ADRF5044.
On the datasheet, it says that the switch has an ideal power-up sequence:
power up GND--->Power up VDD and Vss---->Power up the digital control inputs---->Apply RF input signal
My question is:
(1) power-down sequence is reverse?
(2) My SP16T is in series with antenna. So it will always have RF input signal applying on the switch, no matter it is powered or not. If there is a threshold for power, for example 0 dBm, the switch won't be damaged even if input signal is applyed on it when the switch is powerd down.
(3) the digital control inputs needs to be supplyed after VDD and Vss. So can I design my schimatic as follows:
D1B_IN ,V3,V4 are from MCU,and SW1_V4,SW1_V3 is control inputs to the switch.
On SN74AUP2G125DCUR's datasheet, it says:
So,during power up or power down, its output is in high-impedance. And if I keep D1B_IN(OE/) high until switch is powered on, the control inputs to the switch will be in high-impedance.Is it OK to make control inputs in high-impedance before it is powered on.