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Invalid data interface

Question asked by mario_sun on Jun 6, 2018
Latest reply on Jun 6, 2018 by travisfcollins

AD9361, invalid data interface

 

I am configuring an AD9361 using self-designed software. The write and read register operation are guided by the script generated from AD9361 evaluation software.  The script i am using can be found in the attachment. I checked all of the calibration result, such as BBPLL lock, synthesizer lock, BBDC calibration done. I use enable and txnrx pin to control the transmit and receive behavior. It was mentioned in the data sheet:" In FDD mode, the ENABLE and TXNRX pins can be remapped to serve as real-time RX and TX data transfer control signals. In this mode, the ENABLE pin enables or disables the receive signal path, and the TXNRX pin enables or disables the transmit signal path. In this mode, the ENSM is removed from the system for control of all data flow by these pins. "

 

So it means the ENSM value is invalid in register 0x017. I read the value, the state is Alert. And i observed that the data signal is invalid as shown below. I put data clock from ad9361 into mmcm to generate global clock. So, the state of locked signal seems clock is ok, but frame and data is unchanged.

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