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ERROR: Timing Constraints NOT met! FIR filters integration with the FMCOMMS2 HDL design

Question asked by JohnLiew on Jun 6, 2018
Latest reply on Jun 8, 2018 by lnagy
Hello, I am currently working with FIR filters IP core integration according Integrate FIR filters into the FMCOMMS2 HDL design [Analog Devices Wiki], available from hdl/projects/fmcomms2_fir_filters/zc706/ [GitHub], and I am currently having some issues about Timing Constraints NOT met.  I am not sure if it is something I am doing wrong in my case and any help would be greatly appreciated!
I am using Win 10, Vivado 2016.4, Cygwin64 and downloading the repo as a zip. The project is written for platform  ZC706 + AD-FMCOMMS2, and I can compile it without any error.
As that's the hardware I have, I am trying to build it for ZED + AD-FMCOMMS2. I modified all the zc706 parameters in scripts (include Makfile, tcl) to zed, and also manually compiled axi_i2s_adi and util_i2c_mixer IP cores in the library sub fold. But when I run make, I got the following error messages in log file.
$ tail fmcomms2_zed_fir_filters_vivado.log
open_run: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 2209.121 ; gain = 356.113
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
report_timing_summary: Time (s): cpu = 00:01:06 ; elapsed = 00:00:36 . Memory (MB): peak = 2387.449 ; gain = 178.328
ERROR: Timing Constraints NOT met!
    while executing
"adi_project_run fmcomms2_zed_fir_filters_zed"
    (file "system_project.tcl" line 17)
INFO: [Common 17-206] Exiting Vivado at Tue Jun 05 14:48:26 2018...
Is there any need for additional modification?

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