The data sheets are a little conflicting. I would like to use this part to drive an AD9739 via the ADCLK914 at 2.4GHz. I would also like to generate a 1.2GHz LVDS/analog clock to a national ADC12D1800. The AD9517 would generate the clocks from a 10MHz reference or an external 2.4GHz input. One part of the data sheet shows a 2.95GHz max LVPECL output, 800MHz LVDS. Power curves provided suggest that this will be of sufficient amplitude to drive the ADCLK914. However, other parts of the datasheet say that the PECL output is only up to 1.6GHz and that you must use the divide by 2 to maintain this output frequency.
My application would need to output the 2.4GHz direcly on one differential channel and half that frequency on another. The source of this clock would either be the direct internal clock or a directly coupled external clock of 2.4GHz. Will this part work with sufficient amplitude for each? The National part needs a typical diff input of .6V for the clock.
Will this work?