1) PLL questions:
Can you please provide the ditails of the Ref clock you used for this test (Is it OCXO , TCXO? What is their phase noise)?
Can I improve performance with a reference clock that his phase noise is better?
Is there any chance to have better performance with other PLL mode (if it’s exist)?
2) In the ORX port the maximum power defined as -13dBm (CW).
The SNR is 60dB (2600MHz) .
For our application we need to take 10dB for par and 3 more for calibration.
It means that the maximum power will be -26dBm (LTE).
Is it possible to define the minimum signal for the ORX as:
-73dBm for CW (-13-60=-73) and because we need around 24dB for LTE SNR it will be -49dBm (-73+24=-49dBm).
Is this port is for the DPD? Do I need to design the feedback with some delay or some other aspects?
2) What is the purpose of the SnRX? Can I use it to detect the reverse power of the PA?
What is the minimum detected signal?