ad9361 iio streaming and libiio performs shifts to align data to 12 bits (from 16 bit) is there a reason why there is no option in the fpga hdl to perform this operation in hardware?
This is actually done in the FPGA not IIO. Please see: AXI_AD9361 [Analog Devices Wiki]
Why is libiio then providing the ability to convert to hardware form by shifting every sample of a buffer by an amount and also the ad9361-iiostreaming example show to shift evey sample by 4? Is there a way where I can go from rx to tx without shifting the data by 4 in software?
On the RX side the HDL core does the sign extension. So libiio doesn't need to do it.
On the TX side the samples are expected to be MSB aligned, so you need to do the shift somewhere.
The HDL Core doesn't provide support for it at the moment.
Is there any more input/feedback on this ?
If not, I would mark this as resolved in the next couple of days.
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