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ad9361 iio streaming and libiio performs shifts to align data to 12 bits (from 16 bit) is there a reason why there is no option in the fpga hdl to perform this operation in hardware?

Question asked by jgm on Jun 5, 2018
Latest reply on Aug 10, 2018 by aardelean

ad9361 iio streaming and libiio performs shifts to align data to 12 bits (from 16 bit) is there a reason why there is no option in the fpga hdl to perform this operation in hardware?

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