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AD9172 PCLK Generator Settings

Question asked by bsalz@work on Jun 4, 2018
Latest reply on Jul 6, 2018 by deljones

Hey there,


I have a question about the SERDES PLL configuration for the AD9172. Specifically, I am referencing Figure 48 of the datasheet. We have a MUX that chooses between the direct CLKIN and the PLLCLK.


I know that the SERDES PLL expects 1/40th of the lane rate as an input frequency. I am unsure what the PCLK Generator does or expects from this diagram however. Does it need the 1/40th rate? Does that account or not account for the divide-by-4 block?