I have a question about the SERDES PLL configuration for the AD9172. Specifically, I am referencing Figure 48 of the datasheet. We have a MUX that chooses between the direct CLKIN and the PLLCLK.
I know that the SERDES PLL expects 1/40th of the lane rate as an input frequency. I am unsure what the PCLK Generator does or expects from this diagram however. Does it need the 1/40th rate? Does that account or not account for the divide-by-4 block?