AnsweredAssumed Answered

Configuring AD9361 for PL FIFO mode using device-tree attribute

Question asked by abhinav004 on Jun 4, 2018
Latest reply on Jun 4, 2018 by DragosB

Hi,

I have modified the reference HDL for AD9361-zc7035 to include PL FIFO instead of AXI-DMAC for TX and RX path. After some study on reference device-tree,found that the DMA entries were embedded into cf_ad9361_adc_core_0 for RX  & cf_ad9361_dac_core_0 for TX. Initially, I intended to test the TX path to see if data is being transmitted out correctly, so made the following changes to DT node of DAC core:

 

cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@79024000 {

   compatible = "adi,axi-ad9361-dds-6.00.a";

   reg = <0x79024000 0x1000>;

   clocks = <&adc0_ad9361 13>;

   clock-names = "sampl_clk";

   adi,axi-dds-default-scale = <0>;

   //dmas = <&tx_dma 0>; 

   //dma-names ="tx"

   adi,axi-pl-fifo-enable;

}

The buffer and scan-elements entries from sysfs vanished after commenting the dma section above. However, after passing data from PL FIFO to ad9361 core, the spectrum indicates a single spike indication the default single tone output. It seems this TX core is not able to switch from it's basic single tone output to DAC buffer output. Please indicate any further reference I could use to study more about the HDL DAC core. I have tapped signals b/w PL FIFO and AD9361 HDL core to ensure that data indeed passes to the latter core.

 

P.S. I explored and tried to change the following register of the DAC core without luck. 

REG_CHAN_CNTRL_7 (0x4418)  DAC Channel Control & Status (channel - 0)

 

 

 

Outcomes