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AD9528 : Can be delay SYSREF signal by Coarse Delay block?

Question asked by AkiraO on Jun 4, 2018



I have a question about the function of "8-bit Divider with Coase delay" in AD9528. According to the Figure 27 and Figure 32 in the datasheet of AD9528, we can't control delay of SYSREF signal by "8-bit Divider with Coase delay".  "8-bit Divider with Coase delay" can control delay only PLL1 and PLL2, I think. Is it collect understanding?



Best Regards,