i need to use ad9361 work for tdd mode. so that means i need to output a t/r signal for the amplifier.
i learn that ad9361 have GPO pin to toggle as t/r signal but that maybe not as what we want. so i decide to use fpga to output the t/r signal. we need to set the t/r signal when TX and unset the t/r signal when RX.
the problem is that how much the delay the fpga should impose to the t/r signal. i want to set t/r signal when the fpga start sending data to ad9361 that is when the fpga set the Tx_FRAME pin of ad9361. this is a little ealier than the signal output from antenna port, but that is no problem. the problem is when i unset the t/r signal, because there is delay in the tx chain of ad9361. the manual give an equation to compute the delay of the digital filter part, but what is the delay of the dac and analog part?