I am working on a project to interface a High Speed DAC to the FPGA board using the JESD204B Interfacing. I am trying to figure out how this process can be actually implemented using Xilinx Vivado. I have to have to store the data patterns in a memory and read them out at full speed using the JESD204B interface to the DAC connected through the FMC connector. Can anyone provide me with the HDL code and the technique for this type of implementation. Also, do we make use of the Microblaze soft core processor to store the data patterns in the memory and then transfer them to the DAC through JESD204B interface. I am trying to understand the process and I am finding it difficult.
Any help will be appreciated.