I am working on HDL part of AD9371. We are using GitHub - analogdevicesinc/hdl at dev_tupgrade of HDL branch and using board ZCU102.
We are trying to integrate the System Generator IP with this HDL code and the clock required to operate System Generator IP is 245.76 MHz . So we used clocking wizard IP and provided the input clock of 122.88 MHz from "axi_ad9371_rx_os_clkgen" and tried to generate the output of 245.76 MHz.
But it gives the error :
" [BD 41-238] Port/Pin property FREQ_HZ does not match between /clk_wiz_0/clk_in1(122880000) and /axi_ad9371_rx_os_clkgen/clk_0(100000000.0) "
Please provide us solution to overcome this problem.