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ADV7181D register 0xb1/b2 block length readback BL[13:0]

Question asked by bcmoore001 on May 30, 2018
Latest reply on Jun 6, 2018 by PoornimaSubramani

register 0xb1/b2 block length readback BL[13:0] says it is number of 27mhz clk cycles in 8 lines. But what if we are driving the 7181 with a 28.63636 clk source on pin 22? Is it now the number of 28.63636 cycles?

Can we use the same table valuesthat  the ADV7610 has in its SDTI readbacks for tables 46-47 in its user guide?

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