I'm presently evaluating the AD7177-2 for an extremely demanding application. It seems to have superb noise performance, compared to any other commercial ADCs, as illustrated in Fig. 2 here:
However, I have stumbled upon something - excess 1/f noise, which is dependent on the DC level at the input. I'm sure it originates from the ADC, because I'm providing the DC test voltage from the ADC's own reference. In this configuration, the measurement should be "blind" to its own reference noise.
For now I've found the following details:
- the excess noise depends on the way the VREF+ pin is driven. With internal buffers switched off, optimal results are achieved with a small (20-50 ohm) resistor and 10 nF capacitor very close to the pin.
- there is a lot more excess noise when the internal oscillator is used. With external crystal or external CMOS level-output oscillator, there is less of it (15-20 dB difference)
- To put some rough numbers in:
- at mid-scale (0V, internal short), the intrinsic 1/f noise is about 15 nVRMS/decade, with a corner frequency around 0.05 Hz (!!!)
- at FS (+5V) it's about 130 nVRMS/decade, and the 1/f corner moves to about 1 Hz
I'd like to know whether it's possible to do something about it. The fact that it differs so much with internal oscillator and external crystal makes me think that the remaining part of it is due to the stability of the crystal oscillator. I tried powering the digital part (IOVDD) with a super clean voltage, and there was no difference. Also, different values of capacitors for the crystal made no difference. It works just the same without capacitors, or with the recommended 9 pF. The crystal is the one recommended in the datasheet.
I should mention that the present level of performance is already very high, and it's very likely to meet the specs. However, without this excess 1/f noise it would be truly outstanding.