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AD9164 and ZCU102 - JESD Frame Sync Fails

Question asked by GKoern on May 29, 2018
Latest reply on Jun 3, 2018 by GKoern

We are evaluating the AD9164-FMCC Eval Board in combination with the zcu102 board from Xilinx.
We are setting up the JESD-Configuration on both the Xilinx GTH-transmitter and the AD9164 chip with L=8, M=1, F=1, S=4.
Now we are observing some issues regarding synchronisation:
- If we reset the GTH-Transmitter after reseting/enabling the AD9164 the Code Group Sync (0x470) and the Frame Sync (0x471) are arbitrarily set. (There are even cases when there is Frame Sync without Code Group Sync) But the hardware sync signal is high and not toggling. This state is stable until a new reset of the GTH-Transmitter.
- If we reset/enable the AD9164 after the GTH-Transmitter we get CGS on all eight lanes, but no Frame Sync at all. The hardware sync is also high and not toggling.
I didn't think the order of initialization does matter in the JESD204B protocol.

Is this a known issue? Which way should the initialization be done? Is there a proven way to achieve full ILAS-synchronization?