When we used ADI digital mode conversion chip AD9780, we encountered a relatively difficult problem of on-power reset. The following is the description of the problem:
1. Restoration of AD9780 AD9780 schematic design using website to recommend similar chip AD9783 principle diagram design, it has the electric moment there are two kinds of operation mode can choose (Pin mode and SPI mode), at first we use the Pin mode (corresponding to the CSB Pin 10 k resistance lower, 10 k resistor SDO Pin is pulled, 10 k resistor SDIO Pin down, 10 k resistor Reset Pin down, and the four pins are connected to the FPGA), the electric moment, The normal mode of the chip is used for the reset operation, but the mix mode will be entered several times during multiple power on. After it is charged, FPGA controls the Reset to carry out the Reset operation of pulling up and down, but there will still be time to mix mode. (when the FPGA is not used to control its four pins, the four pins corresponding to FPGA are input state, which should not affect the state of the four pins)
2. The above state is not stable, we modify for SPI AD9780 control mode (corresponding to the 10 k resistor the CSB pin is pulled, 10 k resistor SDO pin is pulled, 10 k resistor SDIO pin down, 10 k resistor Reset pin down, and the four pins are connected to the FPGA, the FPGA corresponding pins to input mode), write in its Reset registers 0 x00 Reset operation, has the phenomenon of Reset, but after Reset, sometimes into the mix mode, It's not normal mode.
3. We read the chip register 0x1F, and the data read out is 0x02. What does this value mean?
To sum up the above phenomenon, no matter which reset mode is adopted, the chip will enter mix mode after multiple switching power operation, and cannot enter normal mode stably.
Please help to analyze whether there is any improper operation in the process of using or whether there is some irrationality in the circuit, so that the restored AD9780 cannot enter normal mode stably