AnsweredAssumed Answered

ad9361 filters

Question asked by fahmed6 on May 28, 2018
Latest reply on May 30, 2018 by fahmed6



I am using zedboard with fscomms3 no-os setup.  I am running ad9361 in 1tx1rx mode. I had a couple of questions related to the tx and rx filters


1. Is there any way to bypass the FIR filters and the interpolation filters (HB1/2/3) in the tx and rx path. searching threads on this topic, seems like whether the filtres are bypassed or not depends on the clk rates in the tx and rx path chains. So i used the following:


{1280000000,40000000,40000000,40000000,40000000,40000000}, // rx_path_clks[6]
{1280000000,40000000,40000000,40000000,40000000,40000000}, // tx_path_clks[6]


but i get the error:

ad9361_validate_trx_clock_chain: Failed - at least one of the clock rates must be equal to the DATA_CLK (lvds) rate


it seems somehow dac_clk rate (i think 80000000 in above case for tx1rx1) has to be included in the path clks. So how do i bypass all interpolation or decimation in the filters? I want my samples to directly go to dac and rescieve them from adc.


2. once the FIR filter taps are defined, how do i enable the FIR filter? in the no-os setup i can see the following:


ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);


this only configures the filters or will it enable it also?