I am using AD9548 with 10MHz from FE5680A as system clock and 1PPS disciplined output from GPS grandmaster device. But minimum phase threshold that I achieved is 10ns at all (0.01Hz bandwidth, 60 margin, 1Hz 3rd pole, 20dB). I observed this lock only several minutes before freq and phase were unlocked again. What is minimum threshold that can be got from real OCXO for example OH100/200/300 from ConnerWinfield or rubidium standard? Does the lock result depend from frequency value of the system clock for example 10MHz, 25MHz or 27MHz? Is there a simple way to estimate time before lock if I know the bandwidth of the DPLL?
What will happen with phase threshold if I use syncronized 1PPS and 10MHz from one source as reference and system clock accordingly?