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Data clock of AD9364

Question asked by s.kannan on May 28, 2018
Latest reply on May 29, 2018 by sripad

I'm using ADI provided No-OS code for our custom board. We are using it for the sampling rate of 768ksps and we generated the filter configuration through AD MATLAB filter wizard. We are configuring the sampling rate to 768ksps by executing the sequence 


ad9361_trx_load_enable_fir(ad9361->phy, rx_fir_config, tx_fir_config);

But when we run init function, our demodulator and FPGA is getting 61.44MHz(we are using LVDS interface) data clock and valid Rx Frame. We don't know why It is giving a valid Rx Frame. 

Is it possible to initialize AD9364 in 768ksps sampling rate?