Recently in the debugging of the ADF4356 PLL chip, the reference input signal is 50MHz, and the PFD after two-fold is 25MHz. However, its output has not been normal. The specific debugging is as follows:
The output of the Muxout pin is verified:
When set to DVdd, the output is 1.77V (not normal);
When set to DGnd, the output is low (0V), normal;
When set to R Divider, the output is high ~1.77V, not normal;
When set to N Divider, the output is a narrow pulse signal of about 4 MHz;
When set to Digital and Analog Lock and Reserved, the output is low; not normal;
When set to 3-state, the output is low. . .
At present, as long as the SPI is written, the signal divided by four is always locked on the 1.13 GHz signal. No matter how the peripheral filter and register are modified, the output signal is basically unchanged. . . .
Please give pointers to the gods. .