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AD9164 Data Structure per Lane for JESD204B

Question asked by mauriziob on May 25, 2018
Latest reply on Jun 6, 2018 by deljones

Good Morning,

I have a design that implement a JESD interface between an FPGA xilinx (using its IP: JESD204B configured in TX mode) to the DAC AD9164.

The AD9164 is configured with LMF = 811 (where I have16 bit sample; 14 bit data resolution). When I generate the transport layer data packet, I understood that with F = 1, the MSB bit (D7) of any octet must change: this means that when I configure the transport layer, the control bits of the sample cannot be both on bits 15 and 14 but I have to put a control bit on D7 (octet n) and the second one to bit D7 (octet n+1) as F=1,  and the Bit 7 of any octet must toggle.

This means that the D7 of any byte must be a toggled control bit.

The DAC AD9164 require to receive data with the following configuration (data sheet Rev C):

Lane 0 : M0S0[15:8]

Lane 1 : M0S0[7:0]

Lane 2 : M0S1[15:8]

Lane 3 : M0S1[7:0]

Lane 4 : M0S2[15:8]

Lane 5 : M0S2[7:0]

Lane 6 : M0S3[15:8]

Lane 7 : M0S3[7:0]

(where M is the single converter; S the four samples in a frame)

This DAC configuration require the 14 bits of data to be received on two lines (i.e.: Line 0: D13 – D8; Line 1: D7 – D0 with D15, D14 available for 2 controls bit).

My question is: how the DAC 9164 is expecting to receive the input data bytes?

In my case: D13 – D0 must be continuous data bits, and control bits on D14, D15 ?

With LMF = 811 I do not understand how I can implement a transport layer that support this configuration without toggle bit#7 any octet.

Could you help me ?

Many thanks in advance