I have a problem:
I use the AD9361 for 2 Tx,MIMO. The sample rate is 61.44MHz, the BandWidth is 50MHz, RF 800MHz.
I use the recommended configs in the document :
AD9361_Reference_Manual_UG-570,Page 102 of 128, Dual Port TDD mode.
I found that : when T1_I[11:0] == T2_I[11:0] T1_Q[11:0] == T2_Q[11:0] in a FB_CLK cycle,the two outputs in RF are right,
when NOT Equal,the two outputs in RF are wrong.
I have modified the config registers(index 0x007),tx delay and tx data delay, when T1_I[11:0] == T2_I[11:0] T1_Q[11:0] == T2_Q[11:0], Reg 0x007's value ,from 0x01,0x02, to 0x0f,the outputs are always right, when NOT equal,the outputs are always wrong.
What's error it may be?