AnsweredAssumed Answered

cache miss despite entry present in table?

Question asked by esfld on Dec 19, 2011
Latest reply on Jan 9, 2012 by KevinL

Hello,

 

I'm using a BF526 on a custom board; VDSP 5.0 update 7.  I've got a VDK + LWIP project and I'm having some cache trouble.

 

I've been running this project with data A,B and instruction cache enabled for some time, but using the default cache settings (no custom cplb table).  Now, the default settings have been giving me some trouble, so I'm trying to create a custom CPLB table, so I can explicitly define the custom external memory range I'm using.

 

The problem I'm having is that near the beginning of my application I call bfrom_SysControl, and as soon as the program attempts to access the ROM space, I get a _cplb_miss_without_replacement error.  RETX shows 0xEF0000EC, and EXCAUSE = 26.  What I don't understand is that I have clearly defined CPLB entries (data and instruction) for the ROM space in the CPLB table.  In fact, I haven't modified these from what their default values were; most of my changes were related to my external address space, so I can't imagine the ROM CPLB settings being different from those generated when I WASN'T using a custom CPLB table, and I did not get this exception in that configuration.  And, I'm not using all of the possible 16 entries in the cache tables, so I know that's not the issue.

 

I'm not sure what to look for next, does anyone have any suggestions?

 

Thanks,

Ethan

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