I have a system with two BF561's connected with SPORT0 mirrored so they can talk to each other:
TFS0 --> RFS0
TSCLK0 --> RSCLK0
DT0PRI --> DR0PRI
DT0SEC --> DR0SEC
(there's 8 wires, both sides see each other the same way).
I have set up the ports to run 32 bits, data dependant frame sync, transmit side internal clock, receive side external clock, frame sync every word:
*pSPORT0_TCLKDIV = 9; // 6.6 MHz NOTE: SCLK = 131.25MHz
*pSPORT0_TFSDIV = 32;
*pSPORT0_TCR2 = 0x011f; // secondary enabled, 32 bits wide
*pSPORT0_RCR2 = 0x011f;
*pSPORT0_TCR1 = 0x0603; // data dependant fs, fs every word, internal clock
*pSPORT0_RCR1 = 0x0401; // external clock, fs every word
With a logic analyzer I can see that the data is transmitted correctly on both processors. But both have the same receive problem. No matter how many times I read the SPORT0_RX register, the RXNE bit never clears! On top of that, I only see the top 16 bits of the secondary transmission repeated in the bottom half. So I send 0x0f5a69c3 but all I see is 0x0f5a0f5a. The FIFO should be only 4 32 bit reads deep, but I can do 8 32 bit reads and get the same bit pattern without clearing the RXNE bit.
The first 32 bit read from the FIFO is the correct data sent on the primary side.
If I try to send 4 32 bit words, then I get a ROVF bit set, but I never see the second primary side data because the FIFO is stuck.
Silicon Rev = 0.5
So far every problem I've had has been easily fixed by flipping a few bits, so I hope the same is true for this problem!
Thanks for any help.