I have the following problem: using an FPGA, I send to the ADV7341 (mounted over the ADV734xEBZ Eval Board) a video stream (single pixel - 30 bit RGB) plus sync signals (VSYNCn e HSYNCn) with a reference clock of 27MHz in PAL format (line period is 64us: 4.67us HSYNC Width + 5.11us HSYNC Back Porch + 53.33us Valid Pixel + 0.889us HSYNC Front Porch). So, the ADV7341 generates correctly the over the CVBS output unless external edge of the frame (see the image tartan.png - I have added on the image a red line to indicate the lack of frame between the expected video and video currently reproduced). What is the matter?
Using the LabView based tool, I have previously configured the ADV7341 using the Table 82 and Table 42 (PAL) reported on the ADV7341 datasheet.
Another bit of information: if I reproduce, using the ADV7341CVBS interface, a ColorBar generates inside my FPGA (see image FPGA_ColorBar.png) and then I reproduceit the ColorBar generates inside the ADV7341 (ADV7341_ColorBar.jpg), the two image seems equal.