My customer use ADP5071 and would like to know how to handle VREF, COMP2, FB2 and SW2 if they don't need negative output ?
Keiichi Okuji @ ADKK
This is what design had to say: make sure that any pins that are high impedance are tied off appropriately, so that they don’t get coupled to any other signals, such as SW1.
VREF: tie to GND.
FB2: should be high impedance if this is an ADJ mode, so tie this off. Appropriate places would be either GND or possibly even VREF, if that’s where it would default to in an application where there was a resistor divider externally. You don’t need to mount the external resistors though.
COMP2: tie it to GND.
SW2: tie it off to either VIN or GND. Tieing it to GND is equivalent to what would happen if you had an inductor mounted externally. That should be ok. Tieing it to VIN would be equivalent to the power switch being on. That’s also ok in this case.
Whatever combination you choose, it would of course be wise to do a quick check to make sure that there is no extra quiescent current or no funny behavior, including during start-up. Note that these kind of cases will likely not have been simulated.
It is not usual to choose ADP5071 and not make use of the inverting regulator. I need to confirm this with design but VREF, COMP2, FB2 and SW2 may be left open while EN2 connected to GND if VNEG is not desired.
Boost regulator products can be found in ADI website in link below:
Thanks for the response. I'm waiting the feed back from design.
I'll talk this with Panasonic.
Panasonic have some products that share similar design but some of products don't need negative power lane so they need to off negative output of ADP5071.
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