1.the jesd204b initialization is ok;
2.when the input is a large signal,the output is multiply of 512;
3.when the input is below -30dBm,the output is 0 or -512;
so i think the LSB 8 bit Iis lost,what is the question?
Thank you for your interest in AD9656.
Do you have SPI control of AD9656? If so, perhaps you could try one of the output digital test patterns (configured by Register 0x0D) to see if you are capturing data as you are expecting.
Are you using the HSC-ADC-EVALEZ FPGA board or are you developing your own capture solution?
we are developing my own capture solution.
with spi control,the digital tese pattern is ok,but in normal work mode,the problem happen.
there are two ad9656 on my board,the fpga is v7485t,and the two ad9656 interconnect with fpga through 4 lane jesd204b.
when in the 204b link initialization,the lsb 9 bits is ok;
when in digital test pattern or in normal work,the lsb 9 bits is all zero,but the msb 7 bit is ok.
I can send you sample FPGA source code, if you think that would help.
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