My understanding so far is the subclass 1 mode of JESD204b require a sysref signal to work.
But i just observed that it is not true. I used an AD9208-3000EBZ board which is attached to VCU118 FPGA board.
The FPGA board is responsible for generating a differential sysref signals which are connected to J200/J4 sysref ports of the AD9208-3000EBZ.
Then, I configured the AD9208 in subclass 1 and managed to capture the counter ramp pattern generated by the two ADC channels on the AD9208-3000EBZ. When i looked the captured data, the counter data of the two ADC channels are well sample aligned (maximum difference is +/-2) even if I disconnected the sysref signal from J200/J4.
So, I guess my question is why i still received the ADC data (and they are even aligned) when there are no sysref signals connected to the AD9208 and it is configured to operate in subclass 1?
Thank you very much.