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ADXL362 CS Hold Time

Question asked by user_name on May 22, 2018
Latest reply on May 24, 2018 by jwang

Before the Rev. D datasheet for the ADXL362, the SPI timing parameter t_CSH (CS Hold Time) was specified as 100 ns minimum, as measured from the rising edge of the last clock to the falling edge of CS. Now, in Rev. D, the CS Hold Time is specified as 20 ns minimum, as measured from the falling edge of the last clock to the falling edge of CS.


Is this correct? It seemed the specification was that the the clock going low and the CS going low at the same instant was not an issue, because t_HIGH (Clock High Time) would be met at the same time as the CS Hold Time. But now it seems the CS must be held for an additional 20ns after the final clock has gone low. Is this really the required timing now? Can anyone explain the change in either the hardware or the specification?

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