I just try implement TWI read/write operation with registers on external slave device without success.
Could you share with example, where I can read/write a registers on external slave TWI (I2C) device.
Thanks in advance.
In master-receive operation, the master must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. This is done by the receiver pulling the SDA line high during the acknowledge clock pulse of the last byte received. This is followed by the The slave-transmitter releasing the data line to allow the master to generate a STOP condition(as seen in the picture attached). There is no additional setup needed for this.
examples are provided by the Hardware Reference Manual and also within VisualDSP++ examples folder.
I2C slave devices often require different procedures to read or write content of their respective registers. This is described by their data sheets or other manuals.
You can find attached a code which was used to interface BF54x processor to an external RAM device.The code is written to write a known set of data to the RAM device and then read it back. You will have to change the slave address(address of the device you want to interface given in the device datasheet) which is defined as a macro in the beginning of the code.
Thanks, I will look into it, do you have any idea how to handle ACK, NACK responce from slave?
These are reflected in the Master Status Register. One point to note is: "ANAK bit if set reflects - The current master transfer was aborted due to the detection of a NAK during the address phase of the transfer. This bit is W1C."
In your code you have
but according to HRM this reagister is RO, therefore why you want to write here?
Looks like a mistake, as those bits are read only.
Yes. All bits in the TWI0_FIFO_STAT register are RO. That line in the code can be commented.
Today I just got a time to look into this, I run your code in configuration TWI0 TX_Master, TWI1 RX_Slave,
I got one interrupt on Master side with *pTWI0_INT_STAT equal to 0x40 which is MERR and MCOMP,
I went into debug and find out that even after a line
I solved above, now I got a very last question in this subject.
In MASTER_READ configuration, when master received last byte he has to send NACK and STOP to SLAVE to terminate service, as I found in HRM STOP is send when DCNT ==0 and it is fine, what about NACK, is it send also in this mode or I have to setup it?
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