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Adjusting FMC-DAQ2 (2016_r2-Linux) sample-rate

Question asked by dglee on May 19, 2018
Latest reply on May 24, 2018 by AdrianC

Hello,

 

I am working with the FMC-DAQ2 reference design for the ZC706. The ADI git-repo is from the 2016.2 tag. I am using Linux with the device-tree settings from here as well:

GitHub - analogdevicesinc/linux at 0a22b1bff3f6475bb6acbeda63303c022561315e 

(xcomm_zynq branch from June 30th 2017)

 

Everything works fine at the 1-Gsps @ 250 MHz FPGA clock-speed but I would like to change the sample-rate speeds to match LTE rates.  The sample-rate requirements are 8 times the LTE bandwidth which would be 245.76  MHz (8x30.72). To simplify things, I think working with one lane rather than four lanes at a time would be ideal. The intended FPGA processing algorithms being implemented are not configured for vector processing. Another approach would be to set the ADC sample at 245.76*4 = 983.04 MHz but only process one of the four samples arriving from the ADC but I don't think that is an elegant solution.

 

I did some reading in several threads and wiki-pages but it is still a little unclear to me how to change these rates but from what I can tell, it seems that these changes will have to be done within the Vivado project. Currently, the Vivado reference design I see a is a “system_util_daq2_xcvr_0” IP core with the following settings:

 

 

It seems that I can adjust number of lanes by adjusting “Tx Num of Lanes” and “Rx Num of Lanes” and the number of ports do change in the IP. It seems that downstream IP would also need to change such as the system_axi_ad9144_jesd_0 number of lanes and data-width to 32-bit if using one-lane.

 

Is changing the clock-rate is as simple as changing the the “Tx Out Div” and “Rx out Div” to 4 to reduce the speed to 250 MHz? Is it possible to be more precise in the clock rate such as the intended 245.76 MHz (or the other option of  983.04 MHz but using all four lanes but only processing one sample)? What do the “Clk25 Div” for Tx and Rx represent? What changes in software are needed (ie: device-tree?) if any?

 

I tried following these threads, however, they make use of No-OS or older versions of this Vivado project which does not have the same "util_adxcvr" IP that I am using so it is still unclear to me on how to proceed

DAQ2: how to change JESD lane rate 

kcu105 + daq2 configuration 

https://ez.analog.com/thread/86782?commentID=266816

AD-FMCDAQ2-EBZ Clocking [Analog Devices Wiki] 

 

 

 

Guidance and help would be appreciated,

Thanks

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