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LTC3300-1 12S current mode communication issue

Question asked by koincidencia on May 18, 2018
Latest reply on May 23, 2018 by WATaylor


We have developed a 12S active cell balancer based on two LTC3300-1. If at least the C6 cell is being charged (bottom IC topmost cell) and any of C7-C12 is being charged (any cell connected to the top IC) then sometimes the Read Balance Status reports all kinds of errors (sec OV, prim OV, OT, all gate drive state is zero) for the top IC after an execution command.


We assume that the current mode communication between the two LTC3300-1 is somehow corrupted during an execution command, then the top IC detects a parity error, which immediately will stop or prevent command activation, which will result in invalid Read Balance Status message (as the datasheet says on page 29: " These 3 bits can only
be logic high following an execute command involving at least one balancer"). Sometimes CRC error also detected during Read Balance Status on the top IC status data.


In the datasheet, on page 26, there is block diagram how does the current mode SPI interface works, but it is not clear how does the communication actually work (what voltage is considered logic low or high). I've attached two oscilloscope figures. Both were measured with low inductance probe (coaxial cable soldered directly on the HV diode pads) with AC coupling on the bottom IC side during a status read operation. The bottom IC V- was used as the signal reference ground. SDOI and SCKO was measured. The "LTC3300-1-statusread-red_SCKO-blue_SDOI-bottomIC-noop" was measured when no cell operation was active, the "LTC3300-1-statusread-red_SCKO-blue_SDOI-bottomIC-C6active" was measured when C6 charging was active. During C6 charging the signal is very noisy.


We tried to replace the HV diodes between the two IC communication lines with shorts, but it did not help. Also tried to put in 1k resistors (we thought that may increase the voltage levels), but it corrupted the communication that there were CRC errors all the time (even without cell operations). The SPI clock speed was 250kHz originally, we also tried to lower it to 125kHz, but it did not make a difference.


Do somebody have any advice how to solve this problem, or what could cause this issue?