The conversion rate appears to be from 0 to 500Ksps and the conversion clock appears to be internal, but I cant find a control reg to set the rate. Oddly missing information in the DS...
correct the part can runs up to 500ksps, however which require an external clock input to drive the SCK pin. Please refer to the timing specification table 4 on the datasheet.
Are you inferring that the SCK runs at 2 speeds? I dont see this spelled out in the data sheet. Do I run SCK at 500,000Hz then ramp it up to clock the data out of the device? The timing diagrams are ambiguous, some of them show SCK transitions during conversion (fig 34), some show SCK dont care partially through conversion (fig 36).
Tsck is 15ns (66MHz) min, far different than 500KHz. Table 4 does not show SCK has a dual role.
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